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sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) 8mb sgram module revision 1.0 april 1999 unbuffered sgram (1mx64 sodimm based on 1mx32 sgram) graphics 64-bit non-ecc/parity 144-pin sodimm
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) revision history revision 0.0 (december 1st, 1998) ? initial draft --- preliminary spec. revision 0.1 (february 1st, 1999) ? remove "burst read single bit write" function. ? change to final spec. revision 1.0 (april 10th, 1999) ? add kmm965(6)g115q(p)-g5 products. ? removed kmm965(6)g115q(p)-g7 @cl2 (115mhz@cl2) part
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) the samsung kmm965(6)g115q(p) is a 1m bit x 64 syn- chronous graphic ram high density memory module. the samsung kmm965(6)g115q(p) consists of two cmos 1m x 32 bit synchronous graphic rams in 100pin qfp packages mounted on a 144pin glass-epoxy substrate. five 0.1uf decoupling capacitors are mounted on the printed circuit board for each synchronous gram. the kmm965(6)g115q(p) is a small outline dual in-line memory module and is intended for mounting into 144-pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable laten- cies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. feature general description kmm965g115q(p) / kmm966g115q(p) sgram sodimm 1mx64 sgram sodimm based on 1mkx32, 2k refresh, 3.3v synchronous graphic rams samsung electronics co. ltd. reserves the right to change products and specifications without notice. ? performance range * km965(6)g115q : based on pqfp component km965(6)g115p : based on tqfp component ? burst mode operation ? block-write and write-per-bit capability ? independent byte operation via dqm0 ~ 7 ? auto & self refresh capability (2048 cycles / 32ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs. cas latency (2, 3) burst length (1, 2, 4, 8 & full page) data scramble (sequential & interleave) ? optional serial pd with eeprom (kmm966g115) ? resistor strapping options for speed and cas latency ? pcb : height(1000mil ) , single sided components part no. max. freq. (t cc ) kmm965(6)g115q(p)-g5 200mhz (5ns) @cl=3 kmm965(6)g115q(p)-g6 166mhz (6ns) @cl=3 kmm965(6)g115q(p)-g7 143mhz (7ns) @cl=3 kmm965(6)g115q(p)-g8 125mhz (8ns) @cl=3 pin names * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin name function a0 ~ a10 address input(multiplexed) ba bank select address dq0 ~ 63 data input / output clk0, *clk1 clock input cke clock enable input cs 0, * cs 1 chip select input ras row address strobe cas column address strobe we write enable dsf define special function dqm0 ~ 7 dqm v dd power supply (3.3v) v ss ground **sda serial address data i/o **sba eeprom device address **scl serial clock rsvd reserved rfu reserved for future use nc no connection pin configurations (front side / back side) pin front pin back pin front pin back pin front pin back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 v ss dq63 dq61 dq59 dq57 v dd dq55 dq53 dq51 dq49 v ss dqm7 dqm5 v dd dq47 dq45 dq43 dq41 v ss dq39 dq37 dq35 dq33 v dd rsvd 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 v ss dq62 dq60 dq58 dq56 v dd dq54 dq52 dq50 dq48 v ss dqm6 dqm4 v dd dq46 dq44 dq42 dq40 v ss dq38 dq36 dq34 dq32 v dd rsvd voltage key 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 dq31 dq29 dq27 dq25 v ss dq23 dq21 dq19 dq17 v dd dqm3 dqm1 v ss dq15 dq13 dq11 dq9 v dd dq7 dq5 dq3 dq1 v ss **sda v dd 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 dq30 dq28 dq26 dq24 v ss dq22 dq20 dq18 dq16 v dd dqm2 dqm0 v ss dq14 dq12 dq10 dq8 v dd dq6 dq4 dq2 dq0 v ss **scl v dd 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 rsvd rsvd v ss dsf rfu rfu v dd * cs 1 ras we v ss *clk1 v dd rsvd a10 ba a7 v ss a5 a3 a1 v dd 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 rsvd rsvd v ss rfu rfu **sba v dd cs0 cas cke v ss clk0 v dd rsvd a9 a8/ap a6 v ss a4 a2 a0 v dd
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) pin configuration description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one clock + t ss prior to new command. disable input buffers for power down in standby. a0 ~ a10 address row / column addresses are multiplexed on the same pins. row address : ra0 ~ ra10, column address : ca0 ~ ca7 ba bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. dqm0 ~ 7 data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) dq0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. dsf define special function enables write per bit, block write and special mode register set. v dd /v ss power supply/ground power and ground for the input buffers and the core logic. three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.timing information for each clock frequency is indicated in the section titled ac charateristics . clock frequency and memory timing cas latency cycle time dq30 dq29 8 ns 1 0 7ns 1 1 6ns 0 0 5ns 0 1 cas latency dq31 3 0 2 and 3 1 resistor strapping options
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) dq0 dq7 functional block diagram v dd vss five 0.1uf capacitors per sgram device to all sgrams cke dsf ras cas we u0 to u1 u0 to u1 u0 to u1 u0 to u1 u0 to u1 clk0 0 w cs0 dq0 dq7 u0 dqm0 dqm0 dq8 dq15 dq8 dq15 dqm1 dqm1 dq16 dq23 dq16 dq23 dqm2 dqm2 dq24 dq31 dq24 dq31 dqm3 dqm3 dq32 dq39 dq0 dq7 u1 dqm0 dqm4 dq40 dq47 dq8 dq15 dqm1 dqm5 dq48 dq55 dq16 dq23 dqm2 dqm6 dq56 dq63 dq24 dq31 dqm3 dqm7 ba a(10:0) u0 to u1 u0 to u1 . . . u0, u1 serial pd sda scl a1 a2 a0 sba v ss * serial pd is optional
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) absolute maximum ratings (voltages referenced to v ss ) parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v) parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v note 4 input high voltage v ih 2.0 3.0 v dd +0.3 v input low voltage v il -0.3 0 0.8 v note 1 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -20 - 20 ua note 2 output leakage current i lo -10 - 10 ua note 3 output loading conditon see figure 1 1. v il (min.) = -1.5v ac (pulse width 5ns) 2. any input 0v v in v dd + 0.3v, all other pins are not under test = 0v. 3. dout is disabled, 0v v out v dd 4. the vdd condition of kmm965(6)g115q(p)-g5/6 is 3.135v~3.6v. note : capacitance (v cc = 3.3v, t a = 25 c, f = 1mhz) parameter symbol min max unit input capacitance (a0 ~ a10, ba) input capacitance ( ras , cas , we , cke, dsf) input capacitance (clk0) input capacitance ( cs 0) input capacitance (dqm0 ~ dqm7) data input/output capacitance (dq0 ~ dq63) c in1 c in2 c in3 c in4 c in5 c out - - - - - - 18 18 18 18 14 15 pf pf pf pf pf pf note :
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) note : 1. unless otherwise notes, input level is cmos(v ih /v il =v ddq /v ssq ) in lvttl. 2. measured with outputs open. address are changed only one time during tcc(min). 3. refresh period is 32ms. address are changed only one time during tcc(min). dc characteristics (recommended operating condition unless otherwise noted, t a = 0 to 70 c, v ih(min) /v il(max) =2.0v/0.8v) parameter symbol test condition cas latency speed unit note -5 -6 -7 -8 operating current (one bank active) i cc1 burst length =1 t rc 3 t rc (min), t cc 3 t cc (min), i o = 0 ma 3 400 360 320 300 ma 2 2 - - - 300 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 15ns 4 ma i cc2 ps cke & clk v il (max), t cc = 4 precharge standby current in non power-down mode i cc2 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 60 ma i cc2 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 30 active standby current in power-down mode i cc3 p cke v il (max), t cc = 15ns 6 ma i cc3 ps cke & v il (max), t cc = 6 active standby current in non power-down mode (one bank active) i cc3 n cke 3 v ih (min), cs 3 v ih (min), t cc = 15ns input signals are changed one time during 30ns 100 ma i cc3 ns cke 3 v ih (min), clk v il (max), t cc = input signals are stable 60 operating current (burst mode) i cc4 i o = 0 ma, page burst all bank activated, t ccd = t ccd (min) 3 580 520 460 400 ma 2 2 - - - 320 refresh current i cc5 t rc 3 t rc (min) 3 400 360 320 300 ma 3 2 - - - 300 self refresh current i cc6 cke 0.2v 4 ma operating current (one bank block write) i cc7 t cc 3 t cc (min), i o =0ma, t bwc (min) 460 400 340 300 ma
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) ac operating test conditions (v dd = 3.3v 0.3v , t a = 0 to 70 c) parameter value ac input levels v ih /v il = 2.4v / 0.4v input timing measurement reference level 1.4v input rise and fall time(see note 3) t r / t f =1ns/ 1ns output timing measurement reference level 1.4v output load condition see fig. 2 3.3v 1200 w 870 w output 30pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma v tt = 1.4v 50 w output 30pf z0=50 w (fig. 2) ac output load circuit (fig. 1) dc output load circuit 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. note : ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -5 -6 -7 -8 unit note min max min max min max min max clk cycle time cas latency=3 t cc 5 1000 6 1000 7 1000 8 1000 ns 1 cas latency=2 - - - 10 clk to valid output delay cas latency=3 t sac - 4.5 - 5.5 - 5.5 - 6 ns 1, 2 cas latency=2 - - - - - - - 6 output data hold time t oh 2 - 2.5 - 2.5 - 2.5 - ns 2 clk high pulse width cas latency=3 t ch 2 - 2.5 - 3 - 3 - ns 3 cas latency=2 - - - - clk low pulse width cas latency=3 t cl 2 - 2.5 - 3 - 3 - ns 3 cas latency=2 - - - - input setup time cas latency=3 t ss 1.5 - 1.5 - 1.75 - 2 - ns 3 cas latency=2 - - - - 2.5 input hold time t sh 1 - 1 - 1 - 1 - ns 3 clk to output in low-z t slz 1 - 1 - 1 - 1 - ns 2 clk to output in hi-z cas latency=3 t shz - 4.5 - 5.5 - 5.5 - 6 ns - cas latency=2 - - - - - - - 6 note : the vdd condition of kmm965(6)g115q(p)-g5/6 is 3.135v~3.6v.
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) operating ac parameter 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. refer to the following clock unit based ac conversion table 2. minimum delay is required to complete write. 3. this parameter means minimum cas to cas delay at block write cycle only. 4. in case of row precharge interrupt, auto precharge and read burst stop. 5. for -6/7/8, trdl =1clk product can be supported within restricted amounts and it will be distinguished by bucket code "nv" note : (ac operating conditions unless otherwise noted) parameter symbol version unit note -5 -6 -7 -8 clk cycle time t cc(min) 5 6 7 8 ns row active to row active delay t rrd(min) 10 12 14 16 ns 1 ras to cas delay t rcd(min) 18 18 18 18 ns 1 row precharge time t rp(min) 18 18 18 18 ns 1 row active time t ras(min) 40 42 49 48 ns 1 t ras(max) 100 us row cycle time t rc ( min ) 65 66 67 68 ns 1 last data in to row precharge t rdl(min) 2 clk 2, 5 last data in to new col.address delay t cdl(min) 1 clk 2 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk block write data-in to pre command t bpl(min) 2 clk block write cycle time t bwc(min) 1 clk 1, 3 mode register set cycle time t mrs(min) 1 clk number of valid output data cas latency=3 2 ea 4 cas latency=2 1 symbol version unit -5 -6 -7 -8 cl 3 - 3 - 3 - 3 2 clk t cc(min) 5 - 6 - 7 - 8 10 ns t rrd(min) 2 clk t rcd(min) 4 - 3 - 3 - 3 2 clk t rp(min) 4 - 3 - 3 - 3 2 clk t ras(min) 8 - 7 - 7 - 6 5 clk t ras(max) 100 us t rc ( min ) 13 - 11 - 10 - 9 7 clk
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we dsf dqm ba a 8 a 10 ,a 9 ,a 7 ~a 0 note register mode register set h x l l l l l x op code 1, 2 special mode register set h 1,2,7 refresh auto refresh h h l l l h l x x 3 self refresh entry l 3 exit l h l h h h x x x 3 h x x x 3 bank active & row addr. write per bit disable h x l l h h l x v row address 4, 5 write per bit enable h 4,5,9 read & column address auto precharge disable h x l h l h l x v l column address (a 0 ~a 7 ) 4 auto precharge enable h 4, 6 write & column address auto precharge disable h x l h l l l x v l column address (a 0 ~a 7 ) 4, 5 auto precharge enable h 4,5,6,9 block write & column auto precharge disable h x l h l l h x v l column address (a 0 ~a 7 ) 4, 5 auto precharge enable h 4,5,6,9 burst stop h x l h h l l x x 7 precharge bank selection h x l l h l l x v l x both banks x h clock suspend or active power down entry h l l h h h x x x h x x x exit l h x x x x x x precharge power down mode entry h l l h h h x x x h x x x exit l h l v v v v x h x x x x dqm h x v x 8 no operation command h x l h h h x x x h x x x 1. op code : operand code a 0 ~ a 10 , ba : program keys. (@mrs) a 5 , a 6 : lmr or lcr select. (@smrs) color register exists only one per dqi which both banks share. so dose mask register. color or mask is loaded into chip through dq pin. 2. mrs can be issued only at both banks precharge state. smrs can be issued only if dq s are idle. a new command can be issued at the next clock of mrs/smrs. note :
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) sgram vs sdram if dsf is low, sgram functionality is identical to sdram functionality . sgram can be used as an unified memory by the appropriate dsf control --> sgram=graphic memory + main memory function mrs bank active write dsf l h l h l h sgram function mrs smrs bank active with write per bit disable bank active with write per bit enable normal write block write 3. auto refresh functions as same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at both precharge state. 4. ba : bank select address. if "low" at read, (block) write, row active and precharge, bank a is selected. if "high" at read, (block) write, row active and precharge, bank b is selected. if a 8 is "high" at row precharge, ba is ignored and both banks are selected. 5. it is determined at row active cycle. whether normal/block write operates in write per bit mode or not. for a bank write, at a bank row active, for b bank write, at b bank row active. terminology : write per bit =i/o mask (block) write with write per bit mode=masked(block) write 6. during burst read or write with auto precharge, new read/(block) write command cannot be issued. another bank read/(block) write command can be issued at t rp after the end of burst. 7. burst stop command is valid only at full page burst length. 8. dqm sampled at positive going edge of a clk. masks the data-in at the very clk(write dqm latency is 0) but makes hi-z state the data-out of 2 clk cycles after.(read dqm latency is 2) 9. graphic features added to sdram s original features. if dsf is tied to low, graphic functions are disabled and chip operates as a 32m sdram with 32 dq s. simplified truth table
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) load color load mask a 6 function a 5 function 0 disable 0 disable 1 enable 1 enable register programmed with mrs (note 1) address ba a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 function rfu tm cas latency bt burst length (note 3) test mode cas latency burst type burst length a 8 a 7 type a 6 a 5 a 4 latency a 3 type a 2 a 1 a 0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 vendor use only 0 0 1 - 1 interleave 0 0 1 2 reserved 1 0 0 1 0 2 0 1 0 4 4 1 1 0 1 1 3 0 1 1 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 256(full) reserved special mode register programmed with smrs address ba a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 function x lc lm x mode register field table to program modes power up sequence sgrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and start clock. must maintain cke= "h", dqm= "h" and the other pins are nop condition at the inputs. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 may be changed. the device is now ready for normal operation. note : 1. if a 9 is high during mrs cycle, "burst read single bit write" function will be enabled. 2. the full column burst(256bit) is available only at sequential mode of burst type. 3. if lc and lm both high(1), data of mask and color register will be unknown.
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) burst sequence (burst length = 4) initial address sequential interleave a 1 a 0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 burst sequence (burst length = 8) initial address sequential interleave a 2 a 1 a 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 pixel to dq mapping(at block write) column address 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 byte a 2 a 1 a 0 i/o 63 - i/o 56 i/o 55 - i/o 48 i/o 47 - i/o 40 i/o 39 - i/o 32 i/o 31 - i/o 24 i/o 23 - i/o 16 i/o 15 - i/o 8 i/o 7 - i/o 0 0 0 0 dq 56 dq 48 dq 40 dq 32 dq 24 dq 16 dq 8 dq 0 0 0 1 dq 57 dq 49 dq 41 dq 33 dq 25 dq 17 dq 9 dq 1 0 1 0 dq 58 dq 50 dq 42 dq 34 dq 26 dq 18 dq 10 dq 2 0 1 1 dq 59 dq 51 dq 43 dq 35 dq 27 dq 19 dq 11 dq 3 1 0 0 dq 60 dq 52 dq 44 dq 36 dq 28 dq 20 dq 12 dq 4 1 0 1 dq 61 dq 53 dq 45 dq 37 dq 29 dq 21 dq 13 dq 5 1 1 0 dq 62 dq 54 dq 46 dq 38 dq 30 dq 22 dq 14 dq 6 1 1 1 dq 63 dq 55 dq 47 dq 39 dq 31 dq 23 dq 15 dq 7
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) package dimensions - proposal (based on jedec std.) 2.66 2.50 units : inches (millimeters) 0.03 typ 0.024 0.001 0.01 max (0.25 max) 0.177 max 0.04 0.0039 (1.00 0.10) 2-r 0.078 min (2.00 min) 0.18 (4.60) 0.75 (19.20) 1.44 (36.80) 0 . 2 4 ( 6 . 0 ) 0.13 0 . 7 9 ( 2 0 . 0 0 ) (0.60 0.05 ) (0.80 typ ) 0 . 1 0 m i n ( 2 . 5 5 m i n ) detail y (3.30) (63.60) (67.60) detail z 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1) 0 . 1 2 5 m i n ( 3 . 2 0 m i n ) (4.5 max) 2- f 0.07 (1.80) 1 . 0 0 ( 2 5 . 4 0 ) 0.16 0.039 (4.00 0.10) 0.083 (2.10) 0.10 (2.50) z y 1.15 (3.70) tolerances : .0059(.15) unless otherwise specified * note 1 : this thickness is when using pqfp package. when using tqfp package, this value is 2.5mmmax. the used device is 1mx32, 32m sgram, 100pin (t)qfp sgram component part no. : km4132g112q : pqfp (height = 3.0mmmax) km4132g112tq : tqfp (height = 1.2mmmax) * note 1
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) serial presence detect information byte # function described function supported hex value note -5 -6 -7 -8 -5 -6 -7 -8 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k bit) 08h 2 fundamental memory type sgram 06h tbd 3 # of row address on this assembly 11 0bh 1 4 # of column address on this assembly 8 08h 1 5 # of module banks on this assembly 1 bank 01h 6 data width of this assembly 64 bits 40h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sgram cycle time from clock @cas latency of 3 5ns 6ns 7ns 8ns 50h 60h 70h 80h 2 10 sgram access time from clock @cas latency of 3 4.5ns 5.5ns 6ns 6ns 45h 55h 60h 60h 2 11 dimm configuraion type non parity 00h 12 refresh rate & type 15.625us, support self refresh 80h 13 primary sgram width x32 20h 14 error checking sgram width none 00h 15 minimum clock delay for back-to-back random column t ccd = 1clk 01h 16 sgram device attributes : burst lengths supported 1, 2, 4, 8 & full page 8fh 17 sgram device attributes : # of banks on sgram device 2 banks 02h 18 sgram device attributes : cas latency 2 & 3 06h 19 sgram device attributes : cs latency 0 clk 01h 20 sgram device attributes : write latency 0 clk 01h 21 sgram module attributes non-buffered, non-registered & redundant addressing 00h 22 sgram device attributes : general +/- 10% voltage tolerance, burst read single bit write precharge all, auto precharge 4eh 23 sgram cycle time @cas latency of 2 - - - 10ns 00h 00h 00h a0h 2 24 sgram access time @cas latency of 2 - - - 6ns 00h 00h 00h 60h 2 25 sgram cycle time @cas latency of 1 - - - - 00h 00h 00h 00h 2 26 sgram access time @cas latency of 1 - - - - 00h 00h 00h 00h 2 27 minimum row precharge time (=t rp ) 18ns 18ns 18ns 18ns 12h 12h 12h 12h 2 28 minimum row active to row active delay (t rrd ) 10ns 12ns 14ns 16ns 0ah 0ch 0eh 10h 2 29 minimum ras to cas delay (=t rcd ) 18ns 18ns 18ns 18ns 12h 12h 12h 12h 2 30 minimum activate to precharge time (=t ras ) 40ns 42ns 49ns 48ns 28h 2ah 31h 30h 2 31 module bank density 1 bank of 8mb 02h 32 address and command signal input setup time (=tss) 1.5ns 1.5ns 1.8ns 2.0ns 15h 15h 18h 20h 2 33 address and command signal input hold time (=tsh) 1ns 1ns 1ns 1ns 10h 10h 10h 10h 2 34 data signal input setup time (=tss) 1.5ns 1.5ns 1.8ns 2.0ns 15h 15h 18h 20h 2 ? serial pd interface protocol : i 2 c ? current sink capability of sda driver 3ma ? maximum clock frequency : 80khz contents ;
sgram module kmm965g115q(p) / kmm966g115q(p) rev. 1.0 (april. 1999) byte # function described function supported hex value note -5 -6 -7 -8 -5 -6 -7 -8 35 data signal input hold time (=tsh) 1ns 1ns 1ns 1ns 10h 10h 10h 10h 2 36 block write size 8 columns 03h 37~61 superset information (maybe used in future) - 00h 62 spd data revision code initial release 00h tbd 63 checksum for bytes 0 ~ 62 - a5h c9h f3h 14h 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (samsung memory) k 4bh 74 manufacturer part # (samsung memory) m 4dh 75 manufacturer part # (memory module) m 4dh 76 manufacturer part # (memory type & edge connector) 9 39h 77 manufacturer part # (data bits) blank 20h 78 ...... manufacturer part # (data bits) 6 36h 79 ...... manufacturer part # (data bits) 6 36h 80 manufacturer part # (mode & operating voltage) g 47h 81 manufacturer part # blank 20h 82 ...... manufacturer part # 1 31h 83 manufacturer part # 1 31h 84 manufacturer part # 5 35h 85 manufacturer part # (component revision) blank(m-die) 20h 86 manufacturer part # (package type) q(pqfp) / p(tqfp) 51h / 50h 87 manufacturer part # (pcb revision) blank 20h 88 manufacturer part # (hyphen) " - " 2dh 89 manufacturer part # (power) g 47h 90 manufacturer part # (minimum cycle time) 5 6 7 8 35h 36h 37h 38h 91 manufacturer revision code (for pcb) blank 20h 92 ...... manufacturer revision code (for component) blank(m-die) 20h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~12 manufacturer specific data (may be used in future) - ffh 126 reserved - ffh 127 reserved - ffh 128+ unused storage locations ffh 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. note :

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